1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) converter, and is preferably applied to a successive approximation A/D converter employing a chopper comparator.
2. Description of the Related Art
In successive approximation A/D converters, consumption of power and voltage therefor can be reduced by using a chopper comparator to compare an analog input voltage with a reference voltage (Japanese Patent Application Laid-open No. 2008-5001). In such successive approximation A/D converters, a D/A converter that generates a reference voltage according to the A/D converted value in more significant bits by using a ladder resistor is provided, and an analog input voltage is sampled and then, is stored in a capacitor. The analog input voltage sampled on the capacitor is compared with a reference voltage successively, and thus, A/D conversion for each bit is successively performed.
In conventional successive approximation A/D converters, charging operation of stray capacitance of a capacitor and comparison thereof are performed successively each time A/D conversion for each bit is performed. Therefore, unfortunately A/D conversion takes time and conversion rate is low.